#ifdef DRAM_LPDDR4_1000M
#define LP4_DENALI_PI_DATA_0    0x00000B00 // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_1    0x00000100 // PI_TCMD_GAP:RW:16:16:=0x0000 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_2    0x00000174 // PI_TDFI_PHYMSTR_MAX:RW:0:32:=0x00000174
#define LP4_DENALI_PI_DATA_3    0x000000BA // PI_TDFI_PHYMSTR_RESP:RW:0:16:=0x00ba
#define LP4_DENALI_PI_DATA_4    0x00000F1C // PI_TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00000f1c
#define LP4_DENALI_PI_DATA_5    0x0000078E // PI_TDFI_PHYMSTR_RESP_F1:RW:0:16:=0x078e
#define LP4_DENALI_PI_DATA_6    0x00001E58 // PI_TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00001e58
#define LP4_DENALI_PI_DATA_7    0x00000F2C // PI_TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x0f2c
#define LP4_DENALI_PI_DATA_8    0x00002D94 // PI_TDFI_PHYMSTR_MAX_F3:RW:0:32:=0x00002d94
#define LP4_DENALI_PI_DATA_9    0x000016CA // PI_TDFI_PHYMSTR_RESP_F3:RW:0:16:=0x16ca
#define LP4_DENALI_PI_DATA_10    0x00003CD0 // PI_TDFI_PHYMSTR_MAX_F4:RW:0:32:=0x00003cd0
#define LP4_DENALI_PI_DATA_11    0x00BA1E68 // PI_TDFI_PHYUPD_RESP:RW:16:16:=0x00ba PI_TDFI_PHYMSTR_RESP_F4:RW:0:16:=0x1e68
#define LP4_DENALI_PI_DATA_12    0x00000200 // PI_TDFI_PHYUPD_TYPE0:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_13    0x00000200 // PI_TDFI_PHYUPD_TYPE1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_14    0x00000200 // PI_TDFI_PHYUPD_TYPE2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_15    0x00000200 // PI_TDFI_PHYUPD_TYPE3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_16    0x0000078E // PI_TDFI_PHYUPD_RESP_F1:RW:0:16:=0x078e
#define LP4_DENALI_PI_DATA_17    0x00000200 // PI_TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_18    0x00000200 // PI_TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_19    0x00000200 // PI_TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_20    0x00000200 // PI_TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_21    0x00000F2C // PI_TDFI_PHYUPD_RESP_F2:RW:0:16:=0x0f2c
#define LP4_DENALI_PI_DATA_22    0x00000200 // PI_TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_23    0x00000200 // PI_TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_24    0x00000200 // PI_TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_25    0x00000200 // PI_TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_26    0x000016CA // PI_TDFI_PHYUPD_RESP_F3:RW:0:16:=0x16ca
#define LP4_DENALI_PI_DATA_27    0x00000200 // PI_TDFI_PHYUPD_TYPE0_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_28    0x00000200 // PI_TDFI_PHYUPD_TYPE1_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_29    0x00000200 // PI_TDFI_PHYUPD_TYPE2_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_30    0x00000200 // PI_TDFI_PHYUPD_TYPE3_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_31    0x00001E68 // PI_TDFI_PHYUPD_RESP_F4:RW:0:16:=0x1e68
#define LP4_DENALI_PI_DATA_32    0x00000200 // PI_TDFI_PHYUPD_TYPE0_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_33    0x00000200 // PI_TDFI_PHYUPD_TYPE1_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_34    0x00000200 // PI_TDFI_PHYUPD_TYPE2_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_35    0x00000200 // PI_TDFI_PHYUPD_TYPE3_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_36    0x00010000 // PI_EXIT_AFTER_INIT_CALVL:RW_D:16:1:=0x01 PI_CONTROL_ERROR_STATUS:RD:0:9:=0x0000
#define LP4_DENALI_PI_DATA_37    0x0000001F // PI_FREQ_MAP:RW:0:32:=0x0000001f
#define LP4_DENALI_PI_DATA_38    0x01000001 // PI_POWER_ON_SEQ_END_ARRAY:RW:24:8:=0x01 PI_POWER_ON_SEQ_BYPASS_ARRAY:RW:16:8:=0x00 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_39    0x00000000 // PI_SEQ1_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_40    0x00000000 // PI_SEQ1_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_41    0x00000000 // PI_SEQ2_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_42    0x00000000 // PI_SEQ2_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_43    0x00000000 // PI_SEQ3_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_44    0x00000000 // PI_SEQ3_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_45    0x00000000 // PI_SEQ4_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_46    0x00000000 // PI_SEQ4_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_47    0x00000000 // PI_SEQ5_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_48    0x00000000 // PI_SEQ5_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_49    0x00000000 // PI_SEQ6_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_50    0x00000000 // PI_SEQ6_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_51    0x00000000 // PI_SEQ7_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_52    0x00000000 // PI_SEQ7_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_53    0x00000000 // PI_SEQ8_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_54    0x00000000 // PI_SEQ8_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_55    0x0F000101 // PI_CS_MAP:RW:24:4:=0x0f RESERVED:RW:16:1:=0x00 PI_SW_RST_N:RW_D:8:1:=0x01 PI_WDT_DISABLE:RW_D:0:1:=0x01
#define LP4_DENALI_PI_DATA_56    0x342D2725 // PI_TDELAY_RDWR_2_BUS_IDLE_F3:RW:24:8:=0x34 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:16:8:=0x2d PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8:=0x27 PI_TDELAY_RDWR_2_BUS_IDLE:RW:0:8:=0x25
#define LP4_DENALI_PI_DATA_57    0x0C04083C // PI_CASLAT_LIN:RW:24:7:=0x0c PI_WRLAT:RW:16:7:=0x04 PI_TMRR:RW:8:4:=0x08 PI_TDELAY_RDWR_2_BUS_IDLE_F4:RW:0:8:=0x3c
#define LP4_DENALI_PI_DATA_58    0x14060C04 // PI_CASLAT_LIN_F2:RW:24:7:=0x14 PI_WRLAT_F2:RW:16:7:=0x06 PI_CASLAT_LIN_F1:RW:8:7:=0x0c PI_WRLAT_F1:RW:0:7:=0x04
#define LP4_DENALI_PI_DATA_59    0x280A1C08 // PI_CASLAT_LIN_F4:RW:24:7:=0x28 PI_WRLAT_F4:RW:16:7:=0x0a PI_CASLAT_LIN_F3:RW:8:7:=0x1c PI_WRLAT_F3:RW:0:7:=0x08
#define LP4_DENALI_PI_DATA_60    0x00000002 // PI_MCAREF_FORWARD_ONLY:RW:16:1:=0x00 PI_AREFRESH:WR:8:1:=0x00 PI_PREAMBLE_SUPPORT:RW:0:2:=0x02
#define LP4_DENALI_PI_DATA_61    0x005D0005 // PI_TREF:RW:16:16:=0x005d PI_TRFC:RW:0:10:=0x0005
#define LP4_DENALI_PI_DATA_62    0x03C7002D // PI_TREF_F1:RW:16:16:=0x03c7 PI_TRFC_F1:RW:0:10:=0x002d
#define LP4_DENALI_PI_DATA_63    0x0796005A // PI_TREF_F2:RW:16:16:=0x0796 PI_TRFC_F2:RW:0:10:=0x005a
#define LP4_DENALI_PI_DATA_64    0x0B650088 // PI_TREF_F3:RW:16:16:=0x0b65 PI_TRFC_F3:RW:0:10:=0x0088
#define LP4_DENALI_PI_DATA_65    0x0F3400B4 // PI_TREF_F4:RW:16:16:=0x0f34 PI_TRFC_F4:RW:0:10:=0x00b4
#define LP4_DENALI_PI_DATA_66    0x00000000 // PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 RESERVED:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_67    0x00000000 // PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00
#define LP4_DENALI_PI_DATA_68    0x00000000 // PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_69    0x00000000 // PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00
#define LP4_DENALI_PI_DATA_70    0x00000000 // PI_SWLVL_RD_SLICE_1:WR:24:1:=0x00 PI_SWLVL_WR_SLICE_1:WR:16:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:8:2:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_71    0x00000000 // PI_SW_WDQLVL_RESP_2:RD:24:2:=0x00 PI_SWLVL_RD_SLICE_2:WR:16:1:=0x00 PI_SWLVL_WR_SLICE_2:WR:8:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_72    0x00000000 // PI_SW_WDQLVL_VREF:RW:24:7:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_RD_SLICE_3:WR:8:1:=0x00 PI_SWLVL_WR_SLICE_3:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_73    0x00000000 // PI_SEQUENTIAL_LVL_REQ:WR:24:1:=0x00 PI_SWLVL_SM2_RD:WR:16:1:=0x00 PI_SWLVL_SM2_WR:WR:8:1:=0x00 PI_SWLVL_SM2_START:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_74    0x01000000 // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_DFI40_POLARITY:RW:16:1:=0x00 PI_SRE_PERIOD_EN:RW:8:1:=0x00 PI_DFS_PERIOD_EN:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_75    0x04040404 // PI_TDFI_CTRL_DELAY_F3:RW_D:24:4:=0x04 PI_TDFI_CTRL_DELAY_F2:RW_D:16:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_76    0x0A000004 // PI_WLDQSEN:RW:24:6:=0x0a PI_WRLVL_CS:RW:16:2:=0x00 PI_WRLVL_REQ:WR:8:1:=0x00 PI_TDFI_CTRL_DELAY_F4:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_77    0x00000128 // PI_WRLVL_INTERVAL:RW:16:16:=0x0000 PI_WRLVL_EN:RW:8:2:=0x01 PI_WLMRD:RW:0:6:=0x28
#define LP4_DENALI_PI_DATA_78    0x00000000 // PI_WRLVL_ROTATE:RW:24:1:=0x00 PI_WRLVL_RESP_MASK:RW:16:4:=0x00 PI_WRLVL_ON_SREF_EXIT:RW:8:1:=0x00 PI_WRLVL_PERIODIC:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_79    0x0003000F // PI_TDFI_WRLVL_EN:RW:16:8:=0x03 PI_WRLVL_ERROR_STATUS:RD:8:2:=0x00 PI_WRLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_80    0x00000018 // PI_TDFI_WRLVL_WW:RW:0:10:=0x0018
#define LP4_DENALI_PI_DATA_81    0x00000000 // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_82    0x00000000 // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_83    0x00060002 // PI_TODTL_2CMD:RW:24:8:=0x00 RESERVED:RW:16:5:=0x06 RESERVED:RW:8:1:=0x00 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02
#define LP4_DENALI_PI_DATA_84    0x00010001 // PI_TODTL_2CMD_F2:RW:24:8:=0x00 PI_ODT_EN_F1:RW:16:1:=0x01 PI_TODTL_2CMD_F1:RW:8:8:=0x00 PI_ODT_EN:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_85    0x00010001 // PI_TODTL_2CMD_F4:RW:24:8:=0x00 PI_ODT_EN_F3:RW:16:1:=0x01 PI_TODTL_2CMD_F3:RW:8:8:=0x00 PI_ODT_EN_F2:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_86    0x01000101 // PI_ODT_RD_MAP_CS0:RW:24:4:=0x01 PI_TODTH_RD:RW:16:4:=0x00 PI_TODTH_WR:RW:8:4:=0x01 PI_ODT_EN_F4:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_87    0x04020201 // PI_ODT_RD_MAP_CS2:RW:24:4:=0x04 PI_ODT_WR_MAP_CS1:RW:16:4:=0x02 PI_ODT_RD_MAP_CS1:RW:8:4:=0x02 PI_ODT_WR_MAP_CS0:RW:0:4:=0x01
#define LP4_DENALI_PI_DATA_88    0x00080804 // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_ODT_WR_MAP_CS3:RW:16:4:=0x08 PI_ODT_RD_MAP_CS3:RW:8:4:=0x08 PI_ODT_WR_MAP_CS2:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_89    0x00000000 // PI_TODTON_MIN_F1:RW:24:4:=0x00 PI_ODTLON_F1:RW:16:4:=0x00 PI_TODTON_MIN:RW:8:4:=0x00 PI_ODTLON:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_90    0x00000000 // PI_TODTON_MIN_F3:RW:24:4:=0x00 PI_ODTLON_F3:RW:16:4:=0x00 PI_TODTON_MIN_F2:RW:8:4:=0x00 PI_ODTLON_F2:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_91    0x03030000 // PI_WR_TO_ODTH_F1:RW:24:6:=0x03 PI_WR_TO_ODTH:RW:16:6:=0x03 PI_TODTON_MIN_F4:RW:8:4:=0x00 PI_ODTLON_F4:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_92    0x04060504 // PI_RD_TO_ODTH:RW:24:6:=0x04 PI_WR_TO_ODTH_F4:RW:16:6:=0x06 PI_WR_TO_ODTH_F3:RW:8:6:=0x05 PI_WR_TO_ODTH_F2:RW:0:6:=0x04
#define LP4_DENALI_PI_DATA_93    0x0F0A0704 // PI_RD_TO_ODTH_F4:RW:24:6:=0x0f PI_RD_TO_ODTH_F3:RW:16:6:=0x0a PI_RD_TO_ODTH_F2:RW:8:6:=0x07 PI_RD_TO_ODTH_F1:RW:0:6:=0x04
#define LP4_DENALI_PI_DATA_94    0x00000000 // PI_RDLVL_SEQ_EN:RW:24:4:=0x00 PI_RDLVL_CS:RW:16:2:=0x00 PI_RDLVL_GATE_REQ:WR:8:1:=0x00 PI_RDLVL_REQ:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_95    0x00000000 // PI_RDLVL_GATE_PERIODIC:RW:24:1:=0x00 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_GATE_SEQ_EN:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_96    0x00000000 // PI_RDLVL_GATE_ROTATE:RW:24:1:=0x00 PI_RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 PI_RDLVL_GATE_ON_SREF_EXIT:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_97    0x001E0F0F // PI_TDFI_RDLVL_RR:RW:16:10:=0x001e PI_RDLVL_GATE_CS_MAP:RW:8:4:=0x0f PI_RDLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_98    0x00000000 // PI_TDFI_RDLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_99    0x01010300 // PI_RDLVL_GATE_EN:RW:24:2:=0x01 PI_RDLVL_EN:RW:16:2:=0x01 PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_100    0x00000000 // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_101    0x00000000 // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_102    0x01000000 // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_103    0x00000101 // PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_104    0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_8:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_105    0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_9:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_106    0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_10:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_107    0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_11:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_108    0x05050001 // PI_RDLAT_ADJ_F1:RW:24:7:=0x05 PI_RDLAT_ADJ:RW:16:7:=0x05 PI_REG_DIMM_ENABLE:RW:8:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_109    0x000e0907 // PI_TDFI_RDDATA_EN:RD:24:7:=0x00 PI_RDLAT_ADJ_F4:RW:16:7:=0x0e PI_RDLAT_ADJ_F3:RW:8:7:=0x09 PI_RDLAT_ADJ_F2:RW:0:7:=0x07
#define LP4_DENALI_PI_DATA_110    0x06040202 // PI_WRLAT_ADJ_F3:RW:24:7:=0x06 PI_WRLAT_ADJ_F2:RW:16:7:=0x04 PI_WRLAT_ADJ_F1:RW:8:7:=0x02 PI_WRLAT_ADJ:RW:0:7:=0x02
#define LP4_DENALI_PI_DATA_111    0x01010008 // PI_TDFI_WRCSLAT_F1:RW:24:7:=0x01 PI_TDFI_WRCSLAT:RW:16:7:=0x01 PI_TDFI_PHY_WRLAT:RD:8:7:=0x00 PI_WRLAT_ADJ_F4:RW:0:7:=0x08
#define LP4_DENALI_PI_DATA_112    0x02020003 // PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F4:RW:16:7:=0x02 PI_TDFI_WRCSLAT_F3:RW:8:7:=0x00 PI_TDFI_WRCSLAT_F2:RW:0:7:=0x03
#define LP4_DENALI_PI_DATA_113    0x00000000 // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:1:=0x00 PI_CALVL_CS:RW:8:2:=0x00 PI_CALVL_REQ:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_114    0x00000003 // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_CALVL_PERIODIC:RW:8:1:=0x00 PI_CALVL_SEQ_EN:RW:0:2:=0x03
#define LP4_DENALI_PI_DATA_115    0x0018170F // PI_TDFI_CALVL_CC:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_116    0x001A0006 // PI_TDFI_CALVL_CC_F1:RW:16:10:=0x001a PI_TDFI_CALVL_CAPTURE:RW:0:10:=0x0006
#define LP4_DENALI_PI_DATA_117    0x001D0008 // PI_TDFI_CALVL_CC_F2:RW:16:10:=0x001d PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x0008
#define LP4_DENALI_PI_DATA_118    0x0020000B // PI_TDFI_CALVL_CC_F3:RW:16:10:=0x0020 PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x000b
#define LP4_DENALI_PI_DATA_119    0x0022000E // PI_TDFI_CALVL_CC_F4:RW:16:10:=0x0022 PI_TDFI_CALVL_CAPTURE_F3:RW:0:10:=0x000e
#define LP4_DENALI_PI_DATA_120    0x00000010 // PI_TDFI_CALVL_CAPTURE_F4:RW:0:10:=0x0010
#define LP4_DENALI_PI_DATA_121    0x00000000 // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_122    0x00000000 // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_123    0x00000100 // PI_CALVL_ERROR_STATUS:RD:16:2:=0x00 PI_CALVL_EN:RW:8:2:=0x01 PI_CALVL_RESP_MASK:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_124    0x140A0000 // PI_TCAMRD:RW:24:6:=0x14 PI_TCACKEL:RW:16:5:=0x0a PI_CALVL_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_125    0x0007010A // PI_TCAENT:RW:16:14:=0x0007 PI_TMRZ:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a
#define LP4_DENALI_PI_DATA_126    0x01003F01 // PI_TMRZ_F2:RW:24:5:=0x01 PI_TCAENT_F1:RW:8:14:=0x003f PI_TMRZ_F1:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_127    0x0002007D // PI_TMRZ_F3:RW:16:5:=0x02 PI_TCAENT_F2:RW:0:14:=0x007d
#define LP4_DENALI_PI_DATA_128    0x000200BC // PI_TMRZ_F4:RW:16:5:=0x02 PI_TCAENT_F3:RW:0:14:=0x00bc
#define LP4_DENALI_PI_DATA_129    0x010A00FA // PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F4:RW:0:14:=0x00fa
#define LP4_DENALI_PI_DATA_130    0x00080100 // PI_TVREF_SHORT:RW:16:10:=0x0008 PI_TDFI_CASEL:RW:8:5:=0x01 PI_TDFI_CACSCA:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_131    0x01000008 // PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG:RW:0:10:=0x0008
#define LP4_DENALI_PI_DATA_132    0x00400040 // PI_TVREF_LONG_F1:RW:16:10:=0x0040 PI_TVREF_SHORT_F1:RW:0:10:=0x0040
#define LP4_DENALI_PI_DATA_133    0x007E0100 // PI_TVREF_SHORT_F2:RW:16:10:=0x007e PI_TDFI_CASEL_F2:RW:8:5:=0x01 PI_TDFI_CACSCA_F2:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_134    0x0100007E // PI_TDFI_CASEL_F3:RW:24:5:=0x01 PI_TDFI_CACSCA_F3:RW:16:5:=0x00 PI_TVREF_LONG_F2:RW:0:10:=0x007e
#define LP4_DENALI_PI_DATA_135    0x00BD00BD // PI_TVREF_LONG_F3:RW:16:10:=0x00bd PI_TVREF_SHORT_F3:RW:0:10:=0x00bd
#define LP4_DENALI_PI_DATA_136    0x00FB0100 // PI_TVREF_SHORT_F4:RW:16:10:=0x00fb PI_TDFI_CASEL_F4:RW:8:5:=0x01 PI_TDFI_CACSCA_F4:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_137    0x1E1A00FB // PI_CALVL_VREF_INITIAL_STOP_POINT:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT:RW:16:7:=0x1a PI_TVREF_LONG_F4:RW:0:10:=0x00fb
#define LP4_DENALI_PI_DATA_138    0x10010204 // PI_TDFI_INIT_START_MIN:RW:24:8:=0x10 PI_CALVL_VREF_DELTA:RW:16:4:=0x01 PI_CALVL_VREF_NORMAL_STEPSIZE:RW:8:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_139    0x06060605 // PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x06 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x06 PI_TDFI_CALVL_STROBE:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05
#define LP4_DENALI_PI_DATA_140    0x02020707 // PI_CALVL_STROBE_NUM:RW:24:5:=0x02 PI_TCKCKEH:RW:16:4:=0x02 PI_TDFI_CALVL_STROBE_F4:RW:8:4:=0x07 PI_TDFI_CALVL_STROBE_F3:RW:0:4:=0x07
#define LP4_DENALI_PI_DATA_141    0x1000C000 // PI_TDFI_INIT_COMPLETE:RW:16:16:=0x1000 PI_TDFI_INIT_START:RW:8:8:=0xc0 PI_SW_CA_TRAIN_VREF:RW:0:7:=0x00
#define LP4_DENALI_PI_DATA_142    0xC01000C0 // PI_TDFI_INIT_START_F2:RW:24:8:=0xc0 PI_TDFI_INIT_COMPLETE_F1:RW:8:16:=0x1000 PI_TDFI_INIT_START_F1:RW:0:8:=0xc0
#define LP4_DENALI_PI_DATA_143    0x00C01000 // PI_TDFI_INIT_START_F3:RW:16:8:=0xc0 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_144    0x00C01000 // PI_TDFI_INIT_START_F4:RW:16:8:=0xc0 PI_TDFI_INIT_COMPLETE_F3:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_145    0x04041000 // PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:24:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:16:8:=0x04 PI_TDFI_INIT_COMPLETE_F4:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_146    0x0B020100 // PI_TCKEHDQS_F1:RW:24:6:=0x0b PI_TCKEHDQS:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_147    0x0112100D // PI_WDQLVL_VREF_EN:RW:24:1:=0x01 PI_TCKEHDQS_F4:RW:16:6:=0x12 PI_TCKEHDQS_F3:RW:8:6:=0x10 PI_TCKEHDQS_F2:RW:0:6:=0x0d
#define LP4_DENALI_PI_DATA_148    0x00004A01 // PI_TDFI_WDQLVL_WR:RW:8:10:=0x004a PI_WDQLVL_BST_NUM:RW:0:3:=0x01
#define LP4_DENALI_PI_DATA_149    0x0000004B // PI_WDQLVL_ROTATE:RW:24:1:=0x00 PI_WDQLVL_RESP_MASK:RW:16:4:=0x00 PI_TDFI_WDQLVL_RW:RW:0:10:=0x004b
#define LP4_DENALI_PI_DATA_150    0x041E1A0F // PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:24:5:=0x04 PI_WDQLVL_VREF_INITIAL_STOP_POINT:RW:16:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT:RW:8:7:=0x1a PI_WDQLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_151    0x00000102 // PI_WDQLVL_REQ:WR:24:1:=0x00 PI_WDQLVL_PERIODIC:RW:16:1:=0x00 PI_WDQLVL_VREF_DELTA:RW:8:4:=0x01 PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:0:5:=0x02
#define LP4_DENALI_PI_DATA_152    0x00003400 // PI_TDFI_WDQLVL_EN:RW:8:8:=0x34 PI_WDQLVL_CS:RW:0:2:=0x00
#define LP4_DENALI_PI_DATA_153    0x00000000 // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_154    0x00000000 // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_155    0x00010000 // PI_WDQLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WDQLVL_EN:RW:16:2:=0x01 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_156    0x31000400 // PI_MR3_DATA_0:RW+:24:8:=0x31 PI_MR2_DATA_0:RW+:16:8:=0x00 PI_MR1_DATA_0:RW+:8:8:=0x04 PI_WDQLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_157    0x044D4D00 // PI_MR1_DATA_F1_0:RW+:24:8:=0x04 PI_MR14_DATA_0:RW+:16:8:=0x4d PI_MR12_DATA_0:RW+:8:8:=0x4d PI_MR11_DATA_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_158    0x4D003100 // PI_MR12_DATA_F1_0:RW+:24:8:=0x4d PI_MR11_DATA_F1_0:RW+:16:8:=0x00 PI_MR3_DATA_F1_0:RW+:8:8:=0x31 PI_MR2_DATA_F1_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_159    0x3109144D // PI_MR3_DATA_F2_0:RW+:24:8:=0x31 PI_MR2_DATA_F2_0:RW+:16:8:=0x09 PI_MR1_DATA_F2_0:RW+:8:8:=0x14 PI_MR14_DATA_F1_0:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_160    0x244D4D00 // PI_MR1_DATA_F3_0:RW+:24:8:=0x24 PI_MR14_DATA_F2_0:RW+:16:8:=0x4d PI_MR12_DATA_F2_0:RW+:8:8:=0x4d PI_MR11_DATA_F2_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_161    0x4D003112 // PI_MR12_DATA_F3_0:RW+:24:8:=0x4d PI_MR11_DATA_F3_0:RW+:16:8:=0x00 PI_MR3_DATA_F3_0:RW+:8:8:=0x31 PI_MR2_DATA_F3_0:RW+:0:8:=0x12
#define LP4_DENALI_PI_DATA_162    0x311B344D // PI_MR3_DATA_F4_0:RW+:24:8:=0x31 PI_MR2_DATA_F4_0:RW+:16:8:=0x1b PI_MR1_DATA_F4_0:RW+:8:8:=0x34 PI_MR14_DATA_F3_0:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_163    0x004D4D00 // PI_MR13_DATA_0:RW+:24:8:=0x00 PI_MR14_DATA_F4_0:RW+:16:8:=0x4d PI_MR12_DATA_F4_0:RW+:8:8:=0x4d PI_MR11_DATA_F4_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_164    0x00310004 // PI_MR11_DATA_1:RW+:24:8:=0x00 PI_MR3_DATA_1:RW+:16:8:=0x31 PI_MR2_DATA_1:RW+:8:8:=0x00 PI_MR1_DATA_1:RW+:0:8:=0x04
#define LP4_DENALI_PI_DATA_165    0x00044D4D // PI_MR2_DATA_F1_1:RW+:24:8:=0x00 PI_MR1_DATA_F1_1:RW+:16:8:=0x04 PI_MR14_DATA_1:RW+:8:8:=0x4d PI_MR12_DATA_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_166    0x4D4D0031 // PI_MR14_DATA_F1_1:RW+:24:8:=0x4d PI_MR12_DATA_F1_1:RW+:16:8:=0x4d PI_MR11_DATA_F1_1:RW+:8:8:=0x00 PI_MR3_DATA_F1_1:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_167    0x00310914 // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR3_DATA_F2_1:RW+:16:8:=0x31 PI_MR2_DATA_F2_1:RW+:8:8:=0x09 PI_MR1_DATA_F2_1:RW+:0:8:=0x14
#define LP4_DENALI_PI_DATA_168    0x12244D4D // PI_MR2_DATA_F3_1:RW+:24:8:=0x12 PI_MR1_DATA_F3_1:RW+:16:8:=0x24 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_169    0x4D4D0031 // PI_MR14_DATA_F3_1:RW+:24:8:=0x4d PI_MR12_DATA_F3_1:RW+:16:8:=0x4d PI_MR11_DATA_F3_1:RW+:8:8:=0x00 PI_MR3_DATA_F3_1:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_170    0x00311B34 // PI_MR11_DATA_F4_1:RW+:24:8:=0x00 PI_MR3_DATA_F4_1:RW+:16:8:=0x31 PI_MR2_DATA_F4_1:RW+:8:8:=0x1b PI_MR1_DATA_F4_1:RW+:0:8:=0x34
#define LP4_DENALI_PI_DATA_171    0x04004D4D // PI_MR1_DATA_2:RW+:24:8:=0x04 PI_MR13_DATA_1:RW+:16:8:=0x00 PI_MR14_DATA_F4_1:RW+:8:8:=0x4d PI_MR12_DATA_F4_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_172    0x4D003100 // PI_MR12_DATA_2:RW+:24:8:=0x4d PI_MR11_DATA_2:RW+:16:8:=0x00 PI_MR3_DATA_2:RW+:8:8:=0x31 PI_MR2_DATA_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_173    0x3100044D // PI_MR3_DATA_F1_2:RW+:24:8:=0x31 PI_MR2_DATA_F1_2:RW+:16:8:=0x00 PI_MR1_DATA_F1_2:RW+:8:8:=0x04 PI_MR14_DATA_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_174    0x144D4D00 // PI_MR1_DATA_F2_2:RW+:24:8:=0x14 PI_MR14_DATA_F1_2:RW+:16:8:=0x4d PI_MR12_DATA_F1_2:RW+:8:8:=0x4d PI_MR11_DATA_F1_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_175    0x4D003109 // PI_MR12_DATA_F2_2:RW+:24:8:=0x4d PI_MR11_DATA_F2_2:RW+:16:8:=0x00 PI_MR3_DATA_F2_2:RW+:8:8:=0x31 PI_MR2_DATA_F2_2:RW+:0:8:=0x09
#define LP4_DENALI_PI_DATA_176    0x3112244D // PI_MR3_DATA_F3_2:RW+:24:8:=0x31 PI_MR2_DATA_F3_2:RW+:16:8:=0x12 PI_MR1_DATA_F3_2:RW+:8:8:=0x24 PI_MR14_DATA_F2_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_177    0x344D4D00 // PI_MR1_DATA_F4_2:RW+:24:8:=0x34 PI_MR14_DATA_F3_2:RW+:16:8:=0x4d PI_MR12_DATA_F3_2:RW+:8:8:=0x4d PI_MR11_DATA_F3_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_178    0x4D00311B // PI_MR12_DATA_F4_2:RW+:24:8:=0x4d PI_MR11_DATA_F4_2:RW+:16:8:=0x00 PI_MR3_DATA_F4_2:RW+:8:8:=0x31 PI_MR2_DATA_F4_2:RW+:0:8:=0x1b
#define LP4_DENALI_PI_DATA_179    0x0004004D // PI_MR2_DATA_3:RW+:24:8:=0x00 PI_MR1_DATA_3:RW+:16:8:=0x04 PI_MR13_DATA_2:RW+:8:8:=0x00 PI_MR14_DATA_F4_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_180    0x4D4D0031 // PI_MR14_DATA_3:RW+:24:8:=0x4d PI_MR12_DATA_3:RW+:16:8:=0x4d PI_MR11_DATA_3:RW+:8:8:=0x00 PI_MR3_DATA_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_181    0x00310004 // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR3_DATA_F1_3:RW+:16:8:=0x31 PI_MR2_DATA_F1_3:RW+:8:8:=0x00 PI_MR1_DATA_F1_3:RW+:0:8:=0x04
#define LP4_DENALI_PI_DATA_182    0x09144D4D // PI_MR2_DATA_F2_3:RW+:24:8:=0x09 PI_MR1_DATA_F2_3:RW+:16:8:=0x14 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_183    0x4D4D0031 // PI_MR14_DATA_F2_3:RW+:24:8:=0x4d PI_MR12_DATA_F2_3:RW+:16:8:=0x4d PI_MR11_DATA_F2_3:RW+:8:8:=0x00 PI_MR3_DATA_F2_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_184    0x00311224 // PI_MR11_DATA_F3_3:RW+:24:8:=0x00 PI_MR3_DATA_F3_3:RW+:16:8:=0x31 PI_MR2_DATA_F3_3:RW+:8:8:=0x12 PI_MR1_DATA_F3_3:RW+:0:8:=0x24
#define LP4_DENALI_PI_DATA_185    0x1B344D4D // PI_MR2_DATA_F4_3:RW+:24:8:=0x1b PI_MR1_DATA_F4_3:RW+:16:8:=0x34 PI_MR14_DATA_F3_3:RW+:8:8:=0x4d PI_MR12_DATA_F3_3:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_186    0x4D4D0031 // PI_MR14_DATA_F4_3:RW+:24:8:=0x4d PI_MR12_DATA_F4_3:RW+:16:8:=0x4d PI_MR11_DATA_F4_3:RW+:8:8:=0x00 PI_MR3_DATA_F4_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_187    0x00010000 // PI_ROW_DIFF:RW:16:3:=0x01 PI_BANK_DIFF:RW:8:2:=0x00 PI_MR13_DATA_3:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_188    0x003F0007 // PI_TFC_F1:RW:16:10:=0x003f PI_TFC:RW:0:10:=0x0007
#define LP4_DENALI_PI_DATA_189    0x00BC007D // PI_TFC_F3:RW:16:10:=0x00bc PI_TFC_F2:RW:0:10:=0x007d
#define LP4_DENALI_PI_DATA_190    0x080800FA // PI_TRTP:RW:24:8:=0x08 PI_TCCD:RW:16:5:=0x08 PI_TFC_F4:RW:0:10:=0x00fa
#define LP4_DENALI_PI_DATA_191    0x040A0404 // PI_TWR:RW:24:6:=0x04 PI_TWTR:RW:16:6:=0x0a PI_TRCD:RW:8:8:=0x04 PI_TRP:RW:0:8:=0x04
#define LP4_DENALI_PI_DATA_192    0x0300070E // PI_TRAS_MIN:RW:24:8:=0x03 PI_TRAS_MAX:RW:0:17:=0x00070e
#define LP4_DENALI_PI_DATA_193    0x010A2001 // PI_TMRW:RW:24:8:=0x01 PI_TMRD:RW:16:6:=0x0a PI_TCCDMW:RW:8:6:=0x20 PI_TDQSCK_MAX:RW:0:4:=0x01
#define LP4_DENALI_PI_DATA_194    0x0A050608 // PI_TWTR_F1:RW:24:6:=0x0a PI_TRCD_F1:RW:16:8:=0x05 PI_TRP_F1:RW:8:8:=0x06 PI_TRTP_F1:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_195    0x0043DE07 // PI_TRAS_MAX_F1:RW:8:17:=0x0043de PI_TWR_F1:RW:0:6:=0x07
#define LP4_DENALI_PI_DATA_196    0x0A20010B // PI_TMRD_F1:RW:24:6:=0x0a PI_TCCDMW_F1:RW:16:6:=0x20 PI_TDQSCK_MAX_F1:RW:8:4:=0x01 PI_TRAS_MIN_F1:RW:0:8:=0x0b
#define LP4_DENALI_PI_DATA_197    0x090B0803 // PI_TRCD_F2:RW:24:8:=0x09 PI_TRP_F2:RW:16:8:=0x0b PI_TRTP_F2:RW:8:8:=0x08 PI_TMRW_F1:RW:0:8:=0x03
#define LP4_DENALI_PI_DATA_198    0x00000B0A // PI_TWR_F2:RW:8:6:=0x0b PI_TWTR_F2:RW:0:6:=0x0a
#define LP4_DENALI_PI_DATA_199    0x150087BD // PI_TRAS_MIN_F2:RW:24:8:=0x15 PI_TRAS_MAX_F2:RW:0:17:=0x0087bd
#define LP4_DENALI_PI_DATA_200    0x050A2002 // PI_TMRW_F2:RW:24:8:=0x05 PI_TMRD_F2:RW:16:6:=0x0a PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x02
#define LP4_DENALI_PI_DATA_201    0x0A0E1008 // PI_TWTR_F3:RW:24:6:=0x0a PI_TRCD_F3:RW:16:8:=0x0e PI_TRP_F3:RW:8:8:=0x10 PI_TRTP_F3:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_202    0x00CBA810 // PI_TRAS_MAX_F3:RW:8:17:=0x00cba8 PI_TWR_F3:RW:0:6:=0x10
#define LP4_DENALI_PI_DATA_203    0x0B200320 // PI_TMRD_F3:RW:24:6:=0x0b PI_TCCDMW_F3:RW:16:6:=0x20 PI_TDQSCK_MAX_F3:RW:8:4:=0x03 PI_TRAS_MIN_F3:RW:0:8:=0x20
#define LP4_DENALI_PI_DATA_204    0x12150808 // PI_TRCD_F4:RW:24:8:=0x12 PI_TRP_F4:RW:16:8:=0x15 PI_TRTP_F4:RW:8:8:=0x08 PI_TMRW_F3:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_205    0x0000140C // PI_TWR_F4:RW:8:6:=0x14 PI_TWTR_F4:RW:0:6:=0x0c
#define LP4_DENALI_PI_DATA_206    0x2A010F7A // PI_TRAS_MIN_F4:RW:24:8:=0x2a PI_TRAS_MAX_F4:RW:0:17:=0x010f7a
#define LP4_DENALI_PI_DATA_207    0x0A0E2004 // PI_TMRW_F4:RW:24:8:=0x0a PI_TMRD_F4:RW:16:6:=0x0e PI_TCCDMW_F4:RW:8:6:=0x20 PI_TDQSCK_MAX_F4:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_208    0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_209    0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_210    0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_211    0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_212    0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_213    0x00000000 // PI_INT_STATUS:RD:0:18:=0x000000
#define LP4_DENALI_PI_DATA_214    0x00000000 // PI_INT_ACK:WR:0:17:=0x000000
#define LP4_DENALI_PI_DATA_215    0x00000000 // PI_INT_MASK:RW:0:18:=0x000000
#define LP4_DENALI_PI_DATA_216    0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_217    0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_218    0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_219    0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_220    0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_221    0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_222    0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_223    0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_224    0x00000000 // PI_BIST_FAIL_ADDR:RD:0:34:=0x00000000
#define LP4_DENALI_PI_DATA_225    0x00000400 // PI_CMD_SWAP_EN:RW_D:24:1:=0x00 PI_LONG_COUNT_MASK:RW:16:5:=0x00 PI_BSTLEN:RW_D:8:5:=0x04 PI_BIST_FAIL_ADDR:RD:0:34:=0x00
#define LP4_DENALI_PI_DATA_226    0x0F0E0D0C // PI_CKE_MUX_3:RW_D:24:4:=0x0f PI_CKE_MUX_2:RW_D:16:4:=0x0e PI_CKE_MUX_1:RW_D:8:4:=0x0d PI_CKE_MUX_0:RW_D:0:4:=0x0c
#define LP4_DENALI_PI_DATA_227    0x0B0A0908 // PI_CS_MUX_3:RW_D:24:4:=0x0b PI_CS_MUX_2:RW_D:16:4:=0x0a PI_CS_MUX_1:RW_D:8:4:=0x09 PI_CS_MUX_0:RW_D:0:4:=0x08
#define LP4_DENALI_PI_DATA_228    0x07060504 // PI_ODT_MUX_3:RW_D:24:4:=0x07 PI_ODT_MUX_2:RW_D:16:4:=0x06 PI_ODT_MUX_1:RW_D:8:4:=0x05 PI_ODT_MUX_0:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_229    0x03020100 // PI_RESET_N_MUX_3:RW_D:24:4:=0x03 PI_RESET_N_MUX_2:RW_D:16:4:=0x02 PI_RESET_N_MUX_1:RW_D:8:4:=0x01 PI_RESET_N_MUX_0:RW_D:0:4:=0x00
#define LP4_DENALI_PI_DATA_230    0x02010000 // PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00
#define LP4_DENALI_PI_DATA_231    0x00000103 // PI_TDFI_CTRLUPD_MIN:RD:16:4:=0x00 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03
#define LP4_DENALI_PI_DATA_232    0x000000BA // PI_TDFI_CTRLUPD_MAX:RW:0:16:=0x00ba
#define LP4_DENALI_PI_DATA_233    0x00000744 // PI_TDFI_CTRLUPD_INTERVAL:RW:0:32:=0x00000744
#define LP4_DENALI_PI_DATA_234    0x0000078E // PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x078e
#define LP4_DENALI_PI_DATA_235    0x00004B8C // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00004b8c
#define LP4_DENALI_PI_DATA_236    0x00000F2C // PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x0f2c
#define LP4_DENALI_PI_DATA_237    0x000097B8 // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000097b8
#define LP4_DENALI_PI_DATA_238    0x000016CA // PI_TDFI_CTRLUPD_MAX_F3:RW:0:16:=0x16ca
#define LP4_DENALI_PI_DATA_239    0x0000E3E4 // PI_TDFI_CTRLUPD_INTERVAL_F3:RW:0:32:=0x0000e3e4
#define LP4_DENALI_PI_DATA_240    0x00001E68 // PI_TDFI_CTRLUPD_MAX_F4:RW:0:16:=0x1e68
#define LP4_DENALI_PI_DATA_241    0x00013010 // PI_TDFI_CTRLUPD_INTERVAL_F4:RW:0:32:=0x00013010
#define LP4_DENALI_PI_DATA_242    0x08000000 // PI_ADDR_SPACE:RW:24:6:=0x08 PI_BIST_RESULT:RD:16:2:=0x00 PI_BIST_GO:WR:8:1:=0x00 PI_UPDATE_ERROR_STATUS:RD:0:7:=0x00
#define LP4_DENALI_PI_DATA_243    0x00000100 // PI_BIST_ADDR_CHECK:RW:8:1:=0x01 PI_BIST_DATA_CHECK:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_244    0x00000000 // PI_BIST_START_ADDRESS:RW:0:34:=0x00000000
#define LP4_DENALI_PI_DATA_245    0x00000000 // PI_BIST_START_ADDRESS:RW:0:34:=0x00
#define LP4_DENALI_PI_DATA_246    0x00000000 // PI_BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP4_DENALI_PI_DATA_247    0x00000000 // PI_BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP4_DENALI_PI_DATA_248    0x00000002 // PI_COL_DIFF:RW:0:4:=0x02
#else
#define LP4_DENALI_PI_DATA_0    	0x00000B00 // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_1    	0x00000100 // PI_TCMD_GAP:RW:16:16:=0x0000 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_2    	0x00000174 // PI_TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00000174
#define LP4_DENALI_PI_DATA_3    	0x000000BA // PI_TDFI_PHYMSTR_RESP_F0:RW:0:16:=0x00ba
#define LP4_DENALI_PI_DATA_4    	0x00000CD8 // PI_TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00000cd8
#define LP4_DENALI_PI_DATA_5    	0x0000066C // PI_TDFI_PHYMSTR_RESP_F1:RW:0:16:=0x066c
#define LP4_DENALI_PI_DATA_6    	0x00002060 // PI_TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00002060
#define LP4_DENALI_PI_DATA_7    	0x00001030 // PI_TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x1030
#define LP4_DENALI_PI_DATA_8    	0x00002B34 // PI_TDFI_PHYMSTR_MAX_F3:RW:0:32:=0x00002b34
#define LP4_DENALI_PI_DATA_9    	0x0000159A // PI_TDFI_PHYMSTR_RESP_F3:RW:0:16:=0x159a
#define LP4_DENALI_PI_DATA_10    	0x000040D4 // PI_TDFI_PHYMSTR_MAX_F4:RW:0:32:=0x000040d4
#define LP4_DENALI_PI_DATA_11    	0x00BA206A // PI_TDFI_PHYUPD_RESP_F0:RW:16:16:=0x00ba PI_TDFI_PHYMSTR_RESP_F4:RW:0:16:=0x206a
#define LP4_DENALI_PI_DATA_12    	0x00000200 // PI_TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_13    	0x00000200 // PI_TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_14    	0x00000200 // PI_TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_15    	0x00000200 // PI_TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_16    	0x0000066C // PI_TDFI_PHYUPD_RESP_F1:RW:0:16:=0x066c
#define LP4_DENALI_PI_DATA_17    	0x00000200 // PI_TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_18    	0x00000200 // PI_TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_19    	0x00000200 // PI_TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_20    	0x00000200 // PI_TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_21    	0x00001030 // PI_TDFI_PHYUPD_RESP_F2:RW:0:16:=0x1030
#define LP4_DENALI_PI_DATA_22    	0x00000200 // PI_TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_23    	0x00000200 // PI_TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_24    	0x00000200 // PI_TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_25    	0x00000200 // PI_TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_26    	0x0000159A // PI_TDFI_PHYUPD_RESP_F3:RW:0:16:=0x159a
#define LP4_DENALI_PI_DATA_27    	0x00000200 // PI_TDFI_PHYUPD_TYPE0_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_28    	0x00000200 // PI_TDFI_PHYUPD_TYPE1_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_29    	0x00000200 // PI_TDFI_PHYUPD_TYPE2_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_30    	0x00000200 // PI_TDFI_PHYUPD_TYPE3_F3:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_31    	0x0000206A // PI_TDFI_PHYUPD_RESP_F4:RW:0:16:=0x206a
#define LP4_DENALI_PI_DATA_32    	0x00000200 // PI_TDFI_PHYUPD_TYPE0_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_33    	0x00000200 // PI_TDFI_PHYUPD_TYPE1_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_34    	0x00000200 // PI_TDFI_PHYUPD_TYPE2_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_35    	0x00000200 // PI_TDFI_PHYUPD_TYPE3_F4:RW:0:32:=0x00000200
#define LP4_DENALI_PI_DATA_36    	0x00010000 // PI_EXIT_AFTER_INIT_CALVL:RW_D:16:1:=0x01 PI_CONTROL_ERROR_STATUS:RD:0:9:=0x0000
#define LP4_DENALI_PI_DATA_37    	0x0000001F // PI_FREQ_MAP:RW:0:32:=0x0000001f
#define LP4_DENALI_PI_DATA_38    	0x01000001 // PI_POWER_ON_SEQ_END_ARRAY:RW:24:8:=0x01 PI_POWER_ON_SEQ_BYPASS_ARRAY:RW:16:8:=0x00 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_39    	0x00000000 // PI_SEQ1_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_40    	0x00000000 // PI_SEQ1_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_41    	0x00000000 // PI_SEQ2_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_42    	0x00000000 // PI_SEQ2_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_43    	0x00000000 // PI_SEQ3_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_44    	0x00000000 // PI_SEQ3_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_45    	0x00000000 // PI_SEQ4_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_46    	0x00000000 // PI_SEQ4_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_47    	0x00000000 // PI_SEQ5_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_48    	0x00000000 // PI_SEQ5_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_49    	0x00000000 // PI_SEQ6_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_50    	0x00000000 // PI_SEQ6_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_51    	0x00000000 // PI_SEQ7_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_52    	0x00000000 // PI_SEQ7_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_53    	0x00000000 // PI_SEQ8_PAT:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_54    	0x00000000 // PI_SEQ8_PAT_MASK:RW:0:28:=0x00000000
#define LP4_DENALI_PI_DATA_55    	0x0F000101 // PI_CS_MAP:RW:24:4:=0x0f RESERVED:RW:16:1:=0x00 PI_SW_RST_N:RW_D:8:1:=0x01 PI_WDT_DISABLE:RW_D:0:1:=0x01
#define LP4_DENALI_PI_DATA_56    	0x332D2725 // PI_TDELAY_RDWR_2_BUS_IDLE_F3:RW:24:8:=0x33 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:16:8:=0x2d PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8:=0x27 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x25
#define LP4_DENALI_PI_DATA_57    	0x0C04083C // PI_CASLAT_LIN_F0:RW:24:7:=0x0c PI_WRLAT_F0:RW:16:7:=0x04 PI_TMRR:RW:8:4:=0x08 PI_TDELAY_RDWR_2_BUS_IDLE_F4:RW:0:8:=0x3c
#define LP4_DENALI_PI_DATA_58    	0x14060C04 // PI_CASLAT_LIN_F2:RW:24:7:=0x14 PI_WRLAT_F2:RW:16:7:=0x06 PI_CASLAT_LIN_F1:RW:8:7:=0x0c PI_WRLAT_F1:RW:0:7:=0x04
#define LP4_DENALI_PI_DATA_59    	0x280A1C08 // PI_CASLAT_LIN_F4:RW:24:7:=0x28 PI_WRLAT_F4:RW:16:7:=0x0a PI_CASLAT_LIN_F3:RW:8:7:=0x1c PI_WRLAT_F3:RW:0:7:=0x08
#define LP4_DENALI_PI_DATA_60    	0x00000002 // PI_MCAREF_FORWARD_ONLY:RW:16:1:=0x00 PI_AREFRESH:WR:8:1:=0x00 PI_PREAMBLE_SUPPORT:RW:0:2:=0x02
#define LP4_DENALI_PI_DATA_61    	0x005D0004 // PI_TREF_F0:RW:16:16:=0x005d PI_TRFC_F0:RW:0:10:=0x0004
#define LP4_DENALI_PI_DATA_62    	0x0336001C // PI_TREF_F1:RW:16:16:=0x0336 PI_TRFC_F1:RW:0:10:=0x001c
#define LP4_DENALI_PI_DATA_63    	0x08180046 // PI_TREF_F2:RW:16:16:=0x0818 PI_TRFC_F2:RW:0:10:=0x0046
#define LP4_DENALI_PI_DATA_64    	0x0ACD005D // PI_TREF_F3:RW:16:16:=0x0acd PI_TRFC_F3:RW:0:10:=0x005d
#define LP4_DENALI_PI_DATA_65    	0x1035008B // PI_TREF_F4:RW:16:16:=0x1035 PI_TRFC_F4:RW:0:10:=0x008b
#define LP4_DENALI_PI_DATA_66    	0x00000000 // PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 RESERVED:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_67    	0x00000000 // PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00
#define LP4_DENALI_PI_DATA_68    	0x00000000 // PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_69    	0x00000000 // PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00
#define LP4_DENALI_PI_DATA_70    	0x00000000 // PI_SWLVL_RD_SLICE_1:WR:24:1:=0x00 PI_SWLVL_WR_SLICE_1:WR:16:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:8:2:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_71    	0x00000000 // PI_SW_WDQLVL_RESP_2:RD:24:2:=0x00 PI_SWLVL_RD_SLICE_2:WR:16:1:=0x00 PI_SWLVL_WR_SLICE_2:WR:8:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_72    	0x00000000 // PI_SW_WDQLVL_VREF:RW:24:7:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_RD_SLICE_3:WR:8:1:=0x00 PI_SWLVL_WR_SLICE_3:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_73    	0x00000000 // PI_SEQUENTIAL_LVL_REQ:WR:24:1:=0x00 PI_SWLVL_SM2_RD:WR:16:1:=0x00 PI_SWLVL_SM2_WR:WR:8:1:=0x00 PI_SWLVL_SM2_START:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_74    	0x01000000 // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_DFI40_POLARITY:RW:16:1:=0x00 PI_SRE_PERIOD_EN:RW:8:1:=0x00 PI_DFS_PERIOD_EN:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_75    	0x04040404 // PI_TDFI_CTRL_DELAY_F3:RW_D:24:4:=0x04 PI_TDFI_CTRL_DELAY_F2:RW_D:16:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F0:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_76    	0x0A000004 // PI_WLDQSEN:RW:24:6:=0x0a PI_WRLVL_CS:RW:16:2:=0x00 PI_WRLVL_REQ:WR:8:1:=0x00 PI_TDFI_CTRL_DELAY_F4:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_77    	0x00000128 // PI_WRLVL_INTERVAL:RW:16:16:=0x0000 PI_WRLVL_EN:RW:8:2:=0x01 PI_WLMRD:RW:0:6:=0x28
#define LP4_DENALI_PI_DATA_78    	0x00000000 // PI_WRLVL_ROTATE:RW:24:1:=0x00 PI_WRLVL_RESP_MASK:RW:16:4:=0x00 PI_WRLVL_ON_SREF_EXIT:RW:8:1:=0x00 PI_WRLVL_PERIODIC:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_79    	0x0003000F // PI_TDFI_WRLVL_EN:RW:16:8:=0x03 PI_WRLVL_ERROR_STATUS:RD:8:2:=0x00 PI_WRLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_80    	0x00000018 // PI_TDFI_WRLVL_WW:RW:0:10:=0x0018
#define LP4_DENALI_PI_DATA_81    	0x00000000 // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_82    	0x00000000 // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_83    	0x00060002 // PI_TODTL_2CMD_F0:RW:24:8:=0x00 RESERVED:RW:16:5:=0x06 RESERVED:RW:8:1:=0x00 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02
#define LP4_DENALI_PI_DATA_84    	0x00010001 // PI_TODTL_2CMD_F2:RW:24:8:=0x00 PI_ODT_EN_F1:RW:16:1:=0x01 PI_TODTL_2CMD_F1:RW:8:8:=0x00 PI_ODT_EN_F0:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_85    	0x00010001 // PI_TODTL_2CMD_F4:RW:24:8:=0x00 PI_ODT_EN_F3:RW:16:1:=0x01 PI_TODTL_2CMD_F3:RW:8:8:=0x00 PI_ODT_EN_F2:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_86    	0x01000101 // PI_ODT_RD_MAP_CS0:RW:24:4:=0x01 PI_TODTH_RD:RW:16:4:=0x00 PI_TODTH_WR:RW:8:4:=0x01 PI_ODT_EN_F4:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_87    	0x04020201 // PI_ODT_RD_MAP_CS2:RW:24:4:=0x04 PI_ODT_WR_MAP_CS1:RW:16:4:=0x02 PI_ODT_RD_MAP_CS1:RW:8:4:=0x02 PI_ODT_WR_MAP_CS0:RW:0:4:=0x01
#define LP4_DENALI_PI_DATA_88    	0x00080804 // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_ODT_WR_MAP_CS3:RW:16:4:=0x08 PI_ODT_RD_MAP_CS3:RW:8:4:=0x08 PI_ODT_WR_MAP_CS2:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_89    	0x00000000 // PI_TODTON_MIN_F1:RW:24:4:=0x00 PI_ODTLON_F1:RW:16:4:=0x00 PI_TODTON_MIN_F0:RW:8:4:=0x00 PI_ODTLON_F0:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_90    	0x00000000 // PI_TODTON_MIN_F3:RW:24:4:=0x00 PI_ODTLON_F3:RW:16:4:=0x00 PI_TODTON_MIN_F2:RW:8:4:=0x00 PI_ODTLON_F2:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_91    	0x03030000 // PI_WR_TO_ODTH_F1:RW:24:6:=0x03 PI_WR_TO_ODTH_F0:RW:16:6:=0x03 PI_TODTON_MIN_F4:RW:8:4:=0x00 PI_ODTLON_F4:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_92    	0x04060504 // PI_RD_TO_ODTH_F0:RW:24:6:=0x04 PI_WR_TO_ODTH_F4:RW:16:6:=0x06 PI_WR_TO_ODTH_F3:RW:8:6:=0x05 PI_WR_TO_ODTH_F2:RW:0:6:=0x04
#define LP4_DENALI_PI_DATA_93    	0x0F0A0704 // PI_RD_TO_ODTH_F4:RW:24:6:=0x0f PI_RD_TO_ODTH_F3:RW:16:6:=0x0a PI_RD_TO_ODTH_F2:RW:8:6:=0x07 PI_RD_TO_ODTH_F1:RW:0:6:=0x04
#define LP4_DENALI_PI_DATA_94    	0x00000000 // PI_RDLVL_SEQ_EN:RW:24:4:=0x00 PI_RDLVL_CS:RW:16:2:=0x00 PI_RDLVL_GATE_REQ:WR:8:1:=0x00 PI_RDLVL_REQ:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_95    	0x00000000 // PI_RDLVL_GATE_PERIODIC:RW:24:1:=0x00 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_GATE_SEQ_EN:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_96    	0x00000000 // PI_RDLVL_GATE_ROTATE:RW:24:1:=0x00 PI_RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 PI_RDLVL_GATE_ON_SREF_EXIT:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_97    	0x001E0F0F // PI_TDFI_RDLVL_RR:RW:16:10:=0x001e PI_RDLVL_GATE_CS_MAP:RW:8:4:=0x0f PI_RDLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_98    	0x00000000 // PI_TDFI_RDLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_99    	0x01010300 // PI_RDLVL_GATE_EN:RW:24:2:=0x01 PI_RDLVL_EN:RW:16:2:=0x01 PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00
#define LP4_DENALI_PI_DATA_100    	0x00000000 // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_101    	0x00000000 // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_102    	0x01000000 // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_103    	0x00000101 // PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_104    	0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_8:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_105    	0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_9:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_106    	0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_10:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_107    	0x55555A5A // PI_LPDDR4_RDLVL_PATTERN_11:RW:0:32:=0x55555a5a
#define LP4_DENALI_PI_DATA_108    	0x05050001 // PI_RDLAT_ADJ_F1:RW:24:7:=0x05 PI_RDLAT_ADJ_F0:RW:16:7:=0x05 PI_REG_DIMM_ENABLE:RW:8:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:0:1:=0x01
#define LP4_DENALI_PI_DATA_109    	0x000F0C07 // PI_TDFI_RDDATA_EN:RD:24:7:=0x00 PI_RDLAT_ADJ_F4:RW:16:7:=0x0d PI_RDLAT_ADJ_F3:RW:8:7:=0x0a PI_RDLAT_ADJ_F2:RW:0:7:=0x07
#define LP4_DENALI_PI_DATA_110    	0x06040202 // PI_WRLAT_ADJ_F3:RW:24:7:=0x06 PI_WRLAT_ADJ_F2:RW:16:7:=0x04 PI_WRLAT_ADJ_F1:RW:8:7:=0x02 PI_WRLAT_ADJ_F0:RW:0:7:=0x02
#define LP4_DENALI_PI_DATA_111    	0x01010008 // PI_TDFI_WRCSLAT_F1:RW:24:7:=0x01 PI_TDFI_WRCSLAT_F0:RW:16:7:=0x01 PI_TDFI_PHY_WRLAT:RD:8:7:=0x00 PI_WRLAT_ADJ_F4:RW:0:7:=0x08
#define LP4_DENALI_PI_DATA_112    	0x02020003 // PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F4:RW:16:7:=0x02 PI_TDFI_WRCSLAT_F3:RW:8:7:=0x00 PI_TDFI_WRCSLAT_F2:RW:0:7:=0x03
#define LP4_DENALI_PI_DATA_113    	0x00000000 // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:1:=0x00 PI_CALVL_CS:RW:8:2:=0x00 PI_CALVL_REQ:WR:0:1:=0x00
#define LP4_DENALI_PI_DATA_114    	0x00000003 // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_CALVL_PERIODIC:RW:8:1:=0x00 PI_CALVL_SEQ_EN:RW:0:2:=0x03
#define LP4_DENALI_PI_DATA_115    	0x0018170F // PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_116    	0x001A0006 // PI_TDFI_CALVL_CC_F1:RW:16:10:=0x001a PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x0006
#define LP4_DENALI_PI_DATA_117    	0x001D0008 // PI_TDFI_CALVL_CC_F2:RW:16:10:=0x001d PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x0008
#define LP4_DENALI_PI_DATA_118    	0x001F000B // PI_TDFI_CALVL_CC_F3:RW:16:10:=0x001f PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x000b
#define LP4_DENALI_PI_DATA_119    	0x0023000D // PI_TDFI_CALVL_CC_F4:RW:16:10:=0x0023 PI_TDFI_CALVL_CAPTURE_F3:RW:0:10:=0x000d
#define LP4_DENALI_PI_DATA_120    	0x00000011 // PI_TDFI_CALVL_CAPTURE_F4:RW:0:10:=0x0011
#define LP4_DENALI_PI_DATA_121    	0x00000000 // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_122    	0x00000000 // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_123    	0x00000100 // PI_CALVL_ERROR_STATUS:RD:16:2:=0x00 PI_CALVL_EN:RW:8:2:=0x01 PI_CALVL_RESP_MASK:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_124    	0x140A0000 // PI_TCAMRD:RW:24:6:=0x14 PI_TCACKEL:RW:16:5:=0x0a PI_CALVL_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_125    	0x0007010A // PI_TCAENT_F0:RW:16:14:=0x0007 PI_TMRZ_F0:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a
#define LP4_DENALI_PI_DATA_126    	0x01003601 // PI_TMRZ_F2:RW:24:5:=0x01 PI_TCAENT_F1:RW:8:14:=0x0036 PI_TMRZ_F1:RW:0:5:=0x01
#define LP4_DENALI_PI_DATA_127    	0x00020086 // PI_TMRZ_F3:RW:16:5:=0x02 PI_TCAENT_F2:RW:0:14:=0x0086
#define LP4_DENALI_PI_DATA_128    	0x000200B2 // PI_TMRZ_F4:RW:16:5:=0x02 PI_TCAENT_F3:RW:0:14:=0x00b2
#define LP4_DENALI_PI_DATA_129    	0x010A010B // PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F4:RW:0:14:=0x010b
#define LP4_DENALI_PI_DATA_130    	0x00080100 // PI_TVREF_SHORT_F0:RW:16:10:=0x0008 PI_TDFI_CASEL_F0:RW:8:5:=0x01 PI_TDFI_CACSCA_F0:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_131    	0x01000008 // PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG_F0:RW:0:10:=0x0008
#define LP4_DENALI_PI_DATA_132    	0x00370037 // PI_TVREF_LONG_F1:RW:16:10:=0x0037 PI_TVREF_SHORT_F1:RW:0:10:=0x0037
#define LP4_DENALI_PI_DATA_133    	0x00870100 // PI_TVREF_SHORT_F2:RW:16:10:=0x0087 PI_TDFI_CASEL_F2:RW:8:5:=0x01 PI_TDFI_CACSCA_F2:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_134    	0x01000087 // PI_TDFI_CASEL_F3:RW:24:5:=0x01 PI_TDFI_CACSCA_F3:RW:16:5:=0x00 PI_TVREF_LONG_F2:RW:0:10:=0x0087
#define LP4_DENALI_PI_DATA_135    	0x00B300B3 // PI_TVREF_LONG_F3:RW:16:10:=0x00b3 PI_TVREF_SHORT_F3:RW:0:10:=0x00b3
#define LP4_DENALI_PI_DATA_136    	0x010C0100 // PI_TVREF_SHORT_F4:RW:16:10:=0x010c PI_TDFI_CASEL_F4:RW:8:5:=0x01 PI_TDFI_CACSCA_F4:RW:0:5:=0x00
#define LP4_DENALI_PI_DATA_137    	0x1E1A010C // PI_CALVL_VREF_INITIAL_STOP_POINT:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT:RW:16:7:=0x1a PI_TVREF_LONG_F4:RW:0:10:=0x010c
#define LP4_DENALI_PI_DATA_138    	0x10010204 // PI_TDFI_INIT_START_MIN:RW:24:8:=0x10 PI_CALVL_VREF_DELTA:RW:16:4:=0x01 PI_CALVL_VREF_NORMAL_STEPSIZE:RW:8:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_139    	0x07060605 // PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x07 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x06 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05
#define LP4_DENALI_PI_DATA_140    	0x02020807 // PI_CALVL_STROBE_NUM:RW:24:5:=0x02 PI_TCKCKEH:RW:16:4:=0x02 PI_TDFI_CALVL_STROBE_F4:RW:8:4:=0x08 PI_TDFI_CALVL_STROBE_F3:RW:0:4:=0x07
#define LP4_DENALI_PI_DATA_141    	0x1000C000 // PI_TDFI_INIT_COMPLETE_F0:RW:16:16:=0x1000 PI_TDFI_INIT_START_F0:RW:8:8:=0xc0 PI_SW_CA_TRAIN_VREF:RW:0:7:=0x00
#define LP4_DENALI_PI_DATA_142    	0xC01000C0 // PI_TDFI_INIT_START_F2:RW:24:8:=0xc0 PI_TDFI_INIT_COMPLETE_F1:RW:8:16:=0x1000 PI_TDFI_INIT_START_F1:RW:0:8:=0xc0
#define LP4_DENALI_PI_DATA_143    	0x00C01000 // PI_TDFI_INIT_START_F3:RW:16:8:=0xc0 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_144    	0x00C01000 // PI_TDFI_INIT_START_F4:RW:16:8:=0xc0 PI_TDFI_INIT_COMPLETE_F3:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_145    	0x04041000 // PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:24:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:16:8:=0x04 PI_TDFI_INIT_COMPLETE_F4:RW:0:16:=0x1000
#define LP4_DENALI_PI_DATA_146    	0x0B020100 // PI_TCKEHDQS_F1:RW:24:6:=0x0b PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_147    	0x0113100E // PI_WDQLVL_VREF_EN:RW:24:1:=0x01 PI_TCKEHDQS_F4:RW:16:6:=0x13 PI_TCKEHDQS_F3:RW:8:6:=0x10 PI_TCKEHDQS_F2:RW:0:6:=0x0e
#define LP4_DENALI_PI_DATA_148    	0x00004A01 // PI_TDFI_WDQLVL_WR:RW:8:10:=0x004a PI_WDQLVL_BST_NUM:RW:0:3:=0x01
#define LP4_DENALI_PI_DATA_149    	0x0000004B // PI_WDQLVL_ROTATE:RW:24:1:=0x00 PI_WDQLVL_RESP_MASK:RW:16:4:=0x00 PI_TDFI_WDQLVL_RW:RW:0:10:=0x004b
#define LP4_DENALI_PI_DATA_150    	0x041E1A0F // PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:24:5:=0x04 PI_WDQLVL_VREF_INITIAL_STOP_POINT:RW:16:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT:RW:8:7:=0x1a PI_WDQLVL_CS_MAP:RW:0:4:=0x0f
#define LP4_DENALI_PI_DATA_151    	0x00000102 // PI_WDQLVL_REQ:WR:24:1:=0x00 PI_WDQLVL_PERIODIC:RW:16:1:=0x00 PI_WDQLVL_VREF_DELTA:RW:8:4:=0x01 PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:0:5:=0x02
#define LP4_DENALI_PI_DATA_152    	0x00003400 // PI_TDFI_WDQLVL_EN:RW:8:8:=0x34 PI_WDQLVL_CS:RW:0:2:=0x00
#define LP4_DENALI_PI_DATA_153    	0x00000000 // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_154    	0x00000000 // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000
#define LP4_DENALI_PI_DATA_155    	0x00010000 // PI_WDQLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WDQLVL_EN:RW:16:2:=0x01 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000
#define LP4_DENALI_PI_DATA_156    	0x31000400 // PI_MR3_DATA_F0_0:RW+:24:8:=0x31 PI_MR2_DATA_F0_0:RW+:16:8:=0x00 PI_MR1_DATA_F0_0:RW+:8:8:=0x04 PI_WDQLVL_ERROR_STATUS:RD:0:2:=0x00
#define LP4_DENALI_PI_DATA_157    	0x044D4D00 // PI_MR1_DATA_F1_0:RW+:24:8:=0x04 PI_MR14_DATA_F0_0:RW+:16:8:=0x4d PI_MR12_DATA_F0_0:RW+:8:8:=0x4d PI_MR11_DATA_F0_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_158    	0x4D003100 // PI_MR12_DATA_F1_0:RW+:24:8:=0x4d PI_MR11_DATA_F1_0:RW+:16:8:=0x00 PI_MR3_DATA_F1_0:RW+:8:8:=0x31 PI_MR2_DATA_F1_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_159    	0x3109144D // PI_MR3_DATA_F2_0:RW+:24:8:=0x31 PI_MR2_DATA_F2_0:RW+:16:8:=0x09 PI_MR1_DATA_F2_0:RW+:8:8:=0x14 PI_MR14_DATA_F1_0:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_160    	0x244D4D00 // PI_MR1_DATA_F3_0:RW+:24:8:=0x24 PI_MR14_DATA_F2_0:RW+:16:8:=0x4d PI_MR12_DATA_F2_0:RW+:8:8:=0x4d PI_MR11_DATA_F2_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_161    	0x4D003112 // PI_MR12_DATA_F3_0:RW+:24:8:=0x4d PI_MR11_DATA_F3_0:RW+:16:8:=0x00 PI_MR3_DATA_F3_0:RW+:8:8:=0x31 PI_MR2_DATA_F3_0:RW+:0:8:=0x12
#define LP4_DENALI_PI_DATA_162    	0x311B344D // PI_MR3_DATA_F4_0:RW+:24:8:=0x31 PI_MR2_DATA_F4_0:RW+:16:8:=0x1b PI_MR1_DATA_F4_0:RW+:8:8:=0x34 PI_MR14_DATA_F3_0:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_163    	0x004D4D00 // PI_MR13_DATA_0:RW+:24:8:=0x00 PI_MR14_DATA_F4_0:RW+:16:8:=0x4d PI_MR12_DATA_F4_0:RW+:8:8:=0x4d PI_MR11_DATA_F4_0:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_164    	0x00310004 // PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR3_DATA_F0_1:RW+:16:8:=0x31 PI_MR2_DATA_F0_1:RW+:8:8:=0x00 PI_MR1_DATA_F0_1:RW+:0:8:=0x04
#define LP4_DENALI_PI_DATA_165    	0x00044D4D // PI_MR2_DATA_F1_1:RW+:24:8:=0x00 PI_MR1_DATA_F1_1:RW+:16:8:=0x04 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_166    	0x4D4D0031 // PI_MR14_DATA_F1_1:RW+:24:8:=0x4d PI_MR12_DATA_F1_1:RW+:16:8:=0x4d PI_MR11_DATA_F1_1:RW+:8:8:=0x00 PI_MR3_DATA_F1_1:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_167    	0x00310914 // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR3_DATA_F2_1:RW+:16:8:=0x31 PI_MR2_DATA_F2_1:RW+:8:8:=0x09 PI_MR1_DATA_F2_1:RW+:0:8:=0x14
#define LP4_DENALI_PI_DATA_168    	0x12244D4D // PI_MR2_DATA_F3_1:RW+:24:8:=0x12 PI_MR1_DATA_F3_1:RW+:16:8:=0x24 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_169    	0x4D4D0031 // PI_MR14_DATA_F3_1:RW+:24:8:=0x4d PI_MR12_DATA_F3_1:RW+:16:8:=0x4d PI_MR11_DATA_F3_1:RW+:8:8:=0x00 PI_MR3_DATA_F3_1:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_170    	0x00311B34 // PI_MR11_DATA_F4_1:RW+:24:8:=0x00 PI_MR3_DATA_F4_1:RW+:16:8:=0x31 PI_MR2_DATA_F4_1:RW+:8:8:=0x1b PI_MR1_DATA_F4_1:RW+:0:8:=0x34
#define LP4_DENALI_PI_DATA_171    	0x04004D4D // PI_MR1_DATA_F0_2:RW+:24:8:=0x04 PI_MR13_DATA_1:RW+:16:8:=0x00 PI_MR14_DATA_F4_1:RW+:8:8:=0x4d PI_MR12_DATA_F4_1:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_172    	0x4D003100 // PI_MR12_DATA_F0_2:RW+:24:8:=0x4d PI_MR11_DATA_F0_2:RW+:16:8:=0x00 PI_MR3_DATA_F0_2:RW+:8:8:=0x31 PI_MR2_DATA_F0_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_173    	0x3100044D // PI_MR3_DATA_F1_2:RW+:24:8:=0x31 PI_MR2_DATA_F1_2:RW+:16:8:=0x00 PI_MR1_DATA_F1_2:RW+:8:8:=0x04 PI_MR14_DATA_F0_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_174    	0x144D4D00 // PI_MR1_DATA_F2_2:RW+:24:8:=0x14 PI_MR14_DATA_F1_2:RW+:16:8:=0x4d PI_MR12_DATA_F1_2:RW+:8:8:=0x4d PI_MR11_DATA_F1_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_175    	0x4D003109 // PI_MR12_DATA_F2_2:RW+:24:8:=0x4d PI_MR11_DATA_F2_2:RW+:16:8:=0x00 PI_MR3_DATA_F2_2:RW+:8:8:=0x31 PI_MR2_DATA_F2_2:RW+:0:8:=0x09
#define LP4_DENALI_PI_DATA_176    	0x3112244D // PI_MR3_DATA_F3_2:RW+:24:8:=0x31 PI_MR2_DATA_F3_2:RW+:16:8:=0x12 PI_MR1_DATA_F3_2:RW+:8:8:=0x24 PI_MR14_DATA_F2_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_177    	0x344D4D00 // PI_MR1_DATA_F4_2:RW+:24:8:=0x34 PI_MR14_DATA_F3_2:RW+:16:8:=0x4d PI_MR12_DATA_F3_2:RW+:8:8:=0x4d PI_MR11_DATA_F3_2:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_178    	0x4D00311B // PI_MR12_DATA_F4_2:RW+:24:8:=0x4d PI_MR11_DATA_F4_2:RW+:16:8:=0x00 PI_MR3_DATA_F4_2:RW+:8:8:=0x31 PI_MR2_DATA_F4_2:RW+:0:8:=0x1b
#define LP4_DENALI_PI_DATA_179    	0x0004004D // PI_MR2_DATA_F0_3:RW+:24:8:=0x00 PI_MR1_DATA_F0_3:RW+:16:8:=0x04 PI_MR13_DATA_2:RW+:8:8:=0x00 PI_MR14_DATA_F4_2:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_180    	0x4D4D0031 // PI_MR14_DATA_F0_3:RW+:24:8:=0x4d PI_MR12_DATA_F0_3:RW+:16:8:=0x4d PI_MR11_DATA_F0_3:RW+:8:8:=0x00 PI_MR3_DATA_F0_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_181    	0x00310004 // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR3_DATA_F1_3:RW+:16:8:=0x31 PI_MR2_DATA_F1_3:RW+:8:8:=0x00 PI_MR1_DATA_F1_3:RW+:0:8:=0x04
#define LP4_DENALI_PI_DATA_182    	0x09144D4D // PI_MR2_DATA_F2_3:RW+:24:8:=0x09 PI_MR1_DATA_F2_3:RW+:16:8:=0x14 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_183    	0x4D4D0031 // PI_MR14_DATA_F2_3:RW+:24:8:=0x4d PI_MR12_DATA_F2_3:RW+:16:8:=0x4d PI_MR11_DATA_F2_3:RW+:8:8:=0x00 PI_MR3_DATA_F2_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_184    	0x00311224 // PI_MR11_DATA_F3_3:RW+:24:8:=0x00 PI_MR3_DATA_F3_3:RW+:16:8:=0x31 PI_MR2_DATA_F3_3:RW+:8:8:=0x12 PI_MR1_DATA_F3_3:RW+:0:8:=0x24
#define LP4_DENALI_PI_DATA_185    	0x1B344D4D // PI_MR2_DATA_F4_3:RW+:24:8:=0x1b PI_MR1_DATA_F4_3:RW+:16:8:=0x34 PI_MR14_DATA_F3_3:RW+:8:8:=0x4d PI_MR12_DATA_F3_3:RW+:0:8:=0x4d
#define LP4_DENALI_PI_DATA_186    	0x4D4D0031 // PI_MR14_DATA_F4_3:RW+:24:8:=0x4d PI_MR12_DATA_F4_3:RW+:16:8:=0x4d PI_MR11_DATA_F4_3:RW+:8:8:=0x00 PI_MR3_DATA_F4_3:RW+:0:8:=0x31
#define LP4_DENALI_PI_DATA_187    	0x00020000 // PI_ROW_DIFF:RW:16:3:=0x02 PI_BANK_DIFF:RW:8:2:=0x00 PI_MR13_DATA_3:RW+:0:8:=0x00
#define LP4_DENALI_PI_DATA_188    	0x00360007 // PI_TFC_F1:RW:16:10:=0x0036 PI_TFC_F0:RW:0:10:=0x0007
#define LP4_DENALI_PI_DATA_189    	0x00B20086 // PI_TFC_F3:RW:16:10:=0x00b2 PI_TFC_F2:RW:0:10:=0x0086
#define LP4_DENALI_PI_DATA_190    	0x0808010B // PI_TRTP_F0:RW:24:8:=0x08 PI_TCCD:RW:16:5:=0x08 PI_TFC_F4:RW:0:10:=0x010b
#define LP4_DENALI_PI_DATA_191    	0x040A0404 // PI_TWR_F0:RW:24:6:=0x04 PI_TWTR_F0:RW:16:6:=0x0a PI_TRCD_F0:RW:8:8:=0x04 PI_TRP_F0:RW:0:8:=0x04
#define LP4_DENALI_PI_DATA_192    	0x0300070E // PI_TRAS_MIN_F0:RW:24:8:=0x03 PI_TRAS_MAX_F0:RW:0:17:=0x00070e
#define LP4_DENALI_PI_DATA_193    	0x010A2001 // PI_TMRW_F0:RW:24:8:=0x01 PI_TMRD_F0:RW:16:6:=0x0a PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01
#define LP4_DENALI_PI_DATA_194    	0x0A040508 // PI_TWTR_F1:RW:24:6:=0x0a PI_TRCD_F1:RW:16:8:=0x04 PI_TRP_F1:RW:8:8:=0x05 PI_TRTP_F1:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_195    	0x0039D206 // PI_TRAS_MAX_F1:RW:8:17:=0x0039d2 PI_TWR_F1:RW:0:6:=0x06
#define LP4_DENALI_PI_DATA_196    	0x0A200109 // PI_TMRD_F1:RW:24:6:=0x0a PI_TCCDMW_F1:RW:16:6:=0x20 PI_TDQSCK_MAX_F1:RW:8:4:=0x01 PI_TRAS_MIN_F1:RW:0:8:=0x09
#define LP4_DENALI_PI_DATA_197    	0x0A0C0803 // PI_TRCD_F2:RW:24:8:=0x0a PI_TRP_F2:RW:16:8:=0x0c PI_TRTP_F2:RW:8:8:=0x08 PI_TMRW_F1:RW:0:8:=0x03
#define LP4_DENALI_PI_DATA_198    	0x00000C0A // PI_TWR_F2:RW:8:6:=0x0c PI_TWTR_F2:RW:0:6:=0x0a
#define LP4_DENALI_PI_DATA_199    	0x170090C9 // PI_TRAS_MIN_F2:RW:24:8:=0x17 PI_TRAS_MAX_F2:RW:0:17:=0x0090c9
#define LP4_DENALI_PI_DATA_200    	0x060A2002 // PI_TMRW_F2:RW:24:8:=0x06 PI_TMRD_F2:RW:16:6:=0x0a PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x02
#define LP4_DENALI_PI_DATA_201    	0x0A0D0F08 // PI_TWTR_F3:RW:24:6:=0x0a PI_TRCD_F3:RW:16:8:=0x0d PI_TRP_F3:RW:8:8:=0x0f PI_TRTP_F3:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_202    	0x00C1140F // PI_TRAS_MAX_F3:RW:8:17:=0x00c114 PI_TWR_F3:RW:0:6:=0x0f
#define LP4_DENALI_PI_DATA_203    	0x0A20031E // PI_TMRD_F3:RW:24:6:=0x0a PI_TCCDMW_F3:RW:16:6:=0x20 PI_TDQSCK_MAX_F3:RW:8:4:=0x03 PI_TRAS_MIN_F3:RW:0:8:=0x1e
#define LP4_DENALI_PI_DATA_204    	0x14170808 // PI_TRCD_F4:RW:24:8:=0x14 PI_TRP_F4:RW:16:8:=0x17 PI_TRTP_F4:RW:8:8:=0x08 PI_TMRW_F3:RW:0:8:=0x08
#define LP4_DENALI_PI_DATA_205    	0x0000160D // PI_TWR_F4:RW:8:6:=0x16 PI_TWTR_F4:RW:0:6:=0x0d
#define LP4_DENALI_PI_DATA_206    	0x2D01216B // PI_TRAS_MIN_F4:RW:24:8:=0x2d PI_TRAS_MAX_F4:RW:0:17:=0x01216b
#define LP4_DENALI_PI_DATA_207    	0x0B0F2004 // PI_TMRW_F4:RW:24:8:=0x0b PI_TMRD_F4:RW:16:6:=0x0f PI_TCCDMW_F4:RW:8:6:=0x20 PI_TDQSCK_MAX_F4:RW:0:4:=0x04
#define LP4_DENALI_PI_DATA_208    	0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_209    	0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_210    	0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_211    	0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_212    	0x00020002 // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02
#define LP4_DENALI_PI_DATA_213    	0x00000000 // PI_INT_STATUS:RD:0:18:=0x000000
#define LP4_DENALI_PI_DATA_214    	0x00000000 // PI_INT_ACK:WR:0:17:=0x000000
#define LP4_DENALI_PI_DATA_215    	0x00000000 // PI_INT_MASK:RW:0:18:=0x000000
#define LP4_DENALI_PI_DATA_216    	0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_217    	0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_218    	0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_219    	0x00000000 // PI_BIST_EXP_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_220    	0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_221    	0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_222    	0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_223    	0x00000000 // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000
#define LP4_DENALI_PI_DATA_224    	0x00000000 // PI_BIST_FAIL_ADDR:RD:0:34:=0x00000000
#define LP4_DENALI_PI_DATA_225    	0x00000400 // PI_CMD_SWAP_EN:RW_D:24:1:=0x00 PI_LONG_COUNT_MASK:RW:16:5:=0x00 PI_BSTLEN:RW_D:8:5:=0x04 PI_BIST_FAIL_ADDR:RD:0:34:=0x00
#define LP4_DENALI_PI_DATA_226    	0x0F0E0D0C // PI_CKE_MUX_3:RW_D:24:4:=0x0f PI_CKE_MUX_2:RW_D:16:4:=0x0e PI_CKE_MUX_1:RW_D:8:4:=0x0d PI_CKE_MUX_0:RW_D:0:4:=0x0c
#define LP4_DENALI_PI_DATA_227    	0x0B0A0908 // PI_CS_MUX_3:RW_D:24:4:=0x0b PI_CS_MUX_2:RW_D:16:4:=0x0a PI_CS_MUX_1:RW_D:8:4:=0x09 PI_CS_MUX_0:RW_D:0:4:=0x08
#define LP4_DENALI_PI_DATA_228    	0x07060504 // PI_ODT_MUX_3:RW_D:24:4:=0x07 PI_ODT_MUX_2:RW_D:16:4:=0x06 PI_ODT_MUX_1:RW_D:8:4:=0x05 PI_ODT_MUX_0:RW_D:0:4:=0x04
#define LP4_DENALI_PI_DATA_229    	0x03020100 // PI_RESET_N_MUX_3:RW_D:24:4:=0x03 PI_RESET_N_MUX_2:RW_D:16:4:=0x02 PI_RESET_N_MUX_1:RW_D:8:4:=0x01 PI_RESET_N_MUX_0:RW_D:0:4:=0x00
#define LP4_DENALI_PI_DATA_230    	0x02010000 // PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00
#define LP4_DENALI_PI_DATA_231    	0x00000103 // PI_TDFI_CTRLUPD_MIN:RD:16:4:=0x00 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03
#define LP4_DENALI_PI_DATA_232    	0x000000BA // PI_TDFI_CTRLUPD_MAX_F0:RW:0:16:=0x00ba
#define LP4_DENALI_PI_DATA_233    	0x00000744 // PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000744
#define LP4_DENALI_PI_DATA_234    	0x0000066C // PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x066c
#define LP4_DENALI_PI_DATA_235    	0x00004038 // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00004038
#define LP4_DENALI_PI_DATA_236    	0x00001030 // PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x1030
#define LP4_DENALI_PI_DATA_237    	0x0000A1E0 // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0000a1e0
#define LP4_DENALI_PI_DATA_238    	0x0000159A // PI_TDFI_CTRLUPD_MAX_F3:RW:0:16:=0x159a
#define LP4_DENALI_PI_DATA_239    	0x0000D804 // PI_TDFI_CTRLUPD_INTERVAL_F3:RW:0:32:=0x0000d804
#define LP4_DENALI_PI_DATA_240    	0x0000206A // PI_TDFI_CTRLUPD_MAX_F4:RW:0:16:=0x206a
#define LP4_DENALI_PI_DATA_241    	0x00014424 // PI_TDFI_CTRLUPD_INTERVAL_F4:RW:0:32:=0x00014424
#define LP4_DENALI_PI_DATA_242    	0x08000000 // PI_ADDR_SPACE:RW:24:6:=0x08 PI_BIST_RESULT:RD:16:2:=0x00 PI_BIST_GO:WR:8:1:=0x00 PI_UPDATE_ERROR_STATUS:RD:0:7:=0x00
#define LP4_DENALI_PI_DATA_243    	0x00000100 // PI_BIST_ADDR_CHECK:RW:8:1:=0x01 PI_BIST_DATA_CHECK:RW:0:1:=0x00
#define LP4_DENALI_PI_DATA_244    	0x00000000 // PI_BIST_START_ADDRESS:RW:0:34:=0x00000000
#define LP4_DENALI_PI_DATA_245    	0x00000000 // PI_BIST_START_ADDRESS:RW:0:34:=0x00
#define LP4_DENALI_PI_DATA_246    	0x00000000 // PI_BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP4_DENALI_PI_DATA_247    	0x00000000 // PI_BIST_DATA_MASK:RW:0:64:=0x00000000
#define LP4_DENALI_PI_DATA_248    	0x00000002 // PI_COL_DIFF:RW:0:4:=0x02
#endif
